課程大綱： 嵌入式系統FPGA設計簡介培訓
What's this programmable logic stuff anyway? History and Architecture
What's this programmable logic stuff anyway? In
Module 1 you learn about the history and architecture of programmable logic devices including
Field Programmable Gate Arrays (FPGAs). You will learn how to describe the difference between an
FPGA, a CPLD, an ASSP, and an ASIC, recite the historical development of programmable logic devices;
and design logic circuits using LUTs. Examples will include designs of digital adders and multipliers in FPGAs.
FPGA Design Tool Flow; An Example DesignIn
Module 2 you will install and use sophisticated FPGA design tools to create an example design.
You will learn the steps in the standard
FPGA design flow, how to use Intel Altera’s Quartus Prime Development Suite to create a pipelined multiplier,
and how to verify the integrity of the design using
the RTL Viewer and by simulation using ModelSim.
Using the TimeQuest timing analyzer, you will analyze the timing of your design to achieve timing closure.
FPGA Architectures: SRAM, FLASH, and Anti-fuseFPGAs are programmable,
and the program resides in a memory which determines how the logic and routing in the device is configured.
In Module 3 you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs.
A survey of modern FPGA architectures will give you the tools to determine which type of
FPGA is the best fit for a design. Architectures will be explored from
the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs.
Programmable logic design using schematic entry design tools
In module 4 you will extend and enhance your design from module 2, completing the design by adding IP blocks,
implementing pin assignments and creating a programming file for
the FPGA. One outcome will be improved design productivity, by use of design techniques like pipelining,
and by the use of system design tools like Qsys,
the system design tool in Quartus Prime.
You will complete a Qsys system design by creating a NIOS II softcore processor design,
which quickly gives you the powerful ability to customize a processor to meet your specific needs.
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